With the advent of less expensive semiconductor memory, modern computer and microcomputer systems have been able to use bit-mapped video displays for the output of data from the system. As is well known, a bit-mapped display requires a memory which can store at least one binary digit (bit) of information for each picture element (pixel) of the display device. Additional bits stored for each pixel provide the capability of the system to render complex images on the video display, such as multi-color images, and background and foreground images, such as a graphics background with textural information overlaid thereupon. The use of bit-mapped storage also allows for data processing operations to easily generate and modify the stored image.
Modern video display devices are often of the raster-scan type, where an electron gun traces horizontal line across the display screen in order to generate the displayed pattern. In order for a displayed raster scan image to continue to be displayed on the video screen, the image must be refreshed at periodic intervals. A common refresh rate for the cathode ray tube video display device is 1/60 of a second, since the refresh operation carried out at that speed is not noticable to the human user of the system. However, as the number of pixels displayed on a screen increases, in order to increase the resolution of the displayed image, more and more bits of information must be accessed from the bit-mapped memory in the refresh interval. If the bit-mapped memory has but a single input and output port, the percentage of time during which the data processing unit can access the bit-mapped memory decreases with the pixel size of the display if the refresh interval remains constant. In addition, the speed of the memory must increase, since more bits must be output during a fixed period of time.
Multiport random access memories have been developed which provide for high-speed output of data to the video display and also for increased accessability of the memory contents to the data processing device. The multiport memories accomplish this by having a first port for random access and update of the memory by the data processing unit of the computer system and a second port for serial output of the memory contents to the video display independent from and asynchronous with the first port, thereby allowing access to the memory contents during output of data to the video display terminal. Examples of multiport random access memories are described in U.S. Pat. No. 4,562,435 (issued Dec. 31, 1985), U.S. Pat. No. 4,639,890 (issued Jan. 27, 1987), and U.S. Pat. No. 4,636,986 (issued Jan. 13, 1987), all assigned to Texas Instruments Incorporated.
The multiport random access memory described in said U.S. Pat. No. 4,636,986 has four random access input/output terminals, and four serial access input/output terminals, so that the single memory device appears to have four memory arrays. This allows a single random access to read or write four data bits simultaneously, with a single address value, and also allows a by-four serial output for purposes of data communication to the video display. An external parallel-to-serial register can then receive the four serial output bits, and shift them to the video display at the display refresh rate; this allows the memory register to shift at one-fourth the rate of the video display, reducing the speed requirements of the semiconductor memory.
Other uses of the by-four organization provide for enhanced image display capabilities. For example, the by-four organization is useful in multi-color displays, since the four bits associated with each address can each constitute a memory "plane". As is well known in the art, a four plane system provides for the storage of a binary code representative of up to sixteen colors for each corresponding pixel of the video display. Another use of the four bits is to use one of the bits to represent text, and the other three bits for representing an eight bit color code for a graphical background; the by-four memory thus facilitates the overlaying of a text message on a graphics image. In such applications, it is useful to be able to modify data (via the random access port) in a subset of planes without modifying the data in the other planes, and without requiring the system to know the value of the data in the non-modified planes. Where a single memory device is used for each plane, the system can easily write to specific planes by controlling the write enable signals going to each chip. The above-referenced U.S. Pat. No. 4,636,986 describes a multiple input/output memory device having a write mask to selectively inhibit the write circuitry for subsets of the four inputs, so that non-selected planes of the video memory may remain unaltered during write operations to the selected planes.
The memory device described in said U.S. Pat. No. 4,636,986 is constructed so that the write mask information is presented to the device upon each occurrence of the row address strobe clock, i.e., at least as often as each change of row address. Advanced graphics systems now utilize extremely wide data buses, however, which necessitates the repeated update of the bit-mapped memory using the same mask information. The updating of a block of memory utilizing such a write mask to be loaded upon each row address strobe cycle requires not only the additional time necessary to set the write mask, but also requires external circuitry to store the write mask value for each repeated loading.
It is therefore an object of this invention to provide a multiple random access input memory capable of retaining a write mask value for multiple memory cycles.
It is another object of this invention to provide such a memory which also has an independent and asynchronous serial output.
It is another object of this invention to provide such a memory having the ability to load a register with the write mask information during a delayed write cycle.
it is another object of this invention to provide such a memory having the ability to retain the write mask information, so that a masked write cycle using a prior mask may be performed after an unmasked write operation.
It is another object of this invention to provide such a memory which contains a data register for storing information to be written to the memory, such as a color code, so that input data need not be provided for each write cycle.
It is yet another object of this invention to provide a dual-port memory which allows the addressing of a plurality of adjacent columns in a single cycle, so that repetitive writing to such adjacent columns can be done in a single memory cycle.
Other objects and advantages of the instant invention will become apparent to those of ordinary skill in the art having reference to the following specification, in combination with the drawings.